The technical field of this invention is memory controllers for small computer systems.
As computer systems have grown more complex, it has become common to employ multiple processors and a wide variety of peripheral devices to transfer data within a chip and from the chip to external devices and visa versa. Such systems almost always have a multiple set of busses separating, for convenience and performance reasons, the communication between similar devices. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between separate buses. Micro-controllers used for this purpose provide bus arbitration which determines, at a given time, which device has control of the bus in question.
A prominent standard bus system has emerged for high performance micro-controller designs. The Advanced Micro-controller Bus Architecture System AMBA(trademark) has been defined by Advanced RISC Machines (ARM) Ltd. (Cambridge, U.K.) and is described in U.S. Pat. No. 5,740,461, dated Apr. 14, 1998. Computer systems of a CISC variety are complex instruction set computers and have total backward compatibility requirements over all versions. RISC (reduced instruction set computer) systems, by contrast, are designed to have simple instruction sets and maximized efficiency of operation. Complex operations are accomplished in RISC machines as well, but they are achieved by using combinations of simple instructions. The RISC machines of ARM Ltd. forming the AMBA architecture are of primary interest here.
FIG. 1 illustrates the standard AMBA(trademark) architecture of prior art, with ARM central processing unit core and AHB Wrapper 101. AMBA has two main busses, an advanced high performance bus AHB 100 and an advanced peripheral bus APB 120 of more moderate performance. In this standard AMBA system the ARM central processing unit core is of moderate performance and does not use an instruction cache. As shown in FIG. 1 the AHB bus is the main memory bus and it couples to RAM 107, ROM 108, external memory interface 102 and direct memory access (DMA) controller 105. FIG. 1 also illustrates one additional high performance peripheral device 130 that will transfer large amounts of data. This peripheral 130 is placed on the high performance AHB bus. This decreases system performance, however, because the Arm central processing unit core cannot have access to memory when this high performance peripheral has control of the bus.
The standard AMBA architecture as illustrated in FIG. 1 employs an AHB-APB bus bridge 109 for controlling the passage of data involving the AHB bus devices, a series of peripheral devices 121 and 122, UART 115, timer 116 and keypad 117. The AHB bus arbiter 105 mediates control of AHB bus 100 between the three masters: ARM central processing unit core 101, direct memory access 105 and high performance peripheral device 130. The AHB-to-APB bus bridge 109 and external memory interface (EMI) 102, RAM 107 and ROM 108 are all slave devices on AHB bus 100.
In summary AMBA, as originally defined, had an ARM central processing unit core, a single high performance bus (AHB) with two or more masters and a more moderate performance peripheral bus APB linked to the AHB bus by the AHB-to-APB bridge. This basic system was created primarily to support cache-based systems or other forms of memory hierarchy.
This invention defines a configurable memory controller (CMC) operating in one of two possible modes for ARM or AHB systems. The configurable memory controller may be operated either in a basic ARM mode from the native ARM core control signals or in the standard AHB mode using AHB bus control signals generated in an AHB wrapper surrounding the ARM central processing unit core.
In the ARM mode, the system has an ARM core with its own ARM bus (no AHB bus or wrapper or arbitration). This system allows only one bus master, the ARM core itself. In this mode the configurable memory controller operates from raw ARM core control signals and is tied directly to ARM core bus. In the ARM mode, the configurable memory controller interfaces with peripherals using a built in peripheral interface to the APB bus.
In the AHB mode, the system has an AHB wrapper surrounding the ARM core as illustrated in FIG. 1. This wrapper is connected to an AHB bus allowing for two or more AHB bus masters with full arbitration. In this mode the configurable memory controller operates from AHB wrapper control signals and is tied directly to the AHB bus. In the AHB mode, the configurable memory controller interfaces with peripherals using the AHB-to-APB bridge.
This configurable memory controller provides the same fundamental memory control as in the AMBA system of FIG. 1. This configurable memory controller also provides a switching mechanism to select between the AHB mode and the ARM mode. Each mode has its own set of special signal definitions.